Modern electronic devices utilize integrated circuits, commonly referred to as "semiconductor chips" which incorporate numerous electronic elements. These chips are mounted on substrates that physically support the chips and electrically interconnect each chip with other elements of the circuit. The substrate may be a printed circuit board or card, or part of a discrete chip package, such as a single chip package (which is also referred to as a semiconductor chip package) or multi-chip package. The chip package is typically incorporated into a larger circuit by being mounted on a printed circuit board. An interconnection between the chip and the chip package is commonly referred to as a "first level" assembly or chip interconnection. An interconnection between the chip package and a printed circuit board or card is commonly referred to as a "second level" interconnection. If the chip is mounted directly on a printed circuit board, the interconnection between the bare chip and the board is intermediate between a first and second level interconnection.
The structures utilized to provide the first level connection between the chip and the substrate of the chip package must accommodate all of the required electrical interconnection to the chip. The center to center distance between one I/O and an adjacent I/O is typically referred to as the pitch. As chip technology advances, the number of first level connections to external circuit elements, commonly referred to as "input-output" or "I/O" connections per chip tends to increase. If the size of the chip remains constant then the pitch must be smaller to accommodate the increased number of I/O's in the same area. Advances in chip technology, however, frequently also allow the production of smaller chips having the same or a greater degree of functionality. Generally, as the chip size decreases and the number of chip contacts increase, the pitch of the second level interconnections becomes smaller and smaller. For example it is not uncommon for chip scale packages, such as the packages disclosed in commonly assigned U.S. Pat. Nos. 5,148,265 and 5,148,266 to have a terminal pitch of 750 .mu.m or less.
In order to make a second level interconnection between a semiconductor chip package having closely spaced I/O's and a printed circuit board, the pitch of the I/O's of the package and the pitch of the connection pads on the printed circuit board must be the same. If they are different the I/O's will not align with the connection pads, and the package and the board will not be electrically interconnected. When a package having terminals in the form of a pin grid array ("PGA") is plugged into a printed circuit board, the apertures on the board must be aligned with and have the same pitch as the pins of the PGA. The same is true of ball grid arrays ("BGA's), where the solder balls of the BGA must be aligned with connection pads on the printed circuit board and with flip chip die where the solder bumps on the bare die must be aligned with connection pads on the printed circuit board. The pitch of many chip scale packages and of some conventional semiconductor chip packages is smaller than the pitch of standard printed circuit boards. For example, printed circuit boards made from FR-4 having connection pads with a pitch of 1000 .mu.m or more are commonly available. If a smaller pitch is needed, the printed circuit board must typically be made of a more esoteric, and expensive material, such as BT resin. It is desirable to have the ability to mount a packages having a small pitch to a standard low cost printed circuit board having a larger pitch.
Even if the availability of lower cost printed circuit boards with small pitches should increase, there is still a need to be able to connect a package having one pitch with a printed circuit board having another pitch. This ability is desirable when one of the components to be mounted to a printed circuit board has a pitch which is different from the pitch of the other components and of the board. Such a situation might occur with high volume components that are most affordable in a particular pitch or with low volume components which may only be available in a limited number of configurations. The semiconductor chip package and translator of the present invention allows a package with one pitch to be mounted to a board having a different pitch.
In addition, it is also desirable to manufacture semiconductor chip packages in wafer level process. A wafer level process can provide significant advantages in handling and process chips. However, wafer-level processing is not normally used to form fan-out or fan-in/fan-out structures. A wafer level package having a fan-out structure will intrinsically be larger than its silicon die and would therefor waste silicon and reduce the number of die per wafer. These economic concerns usually rule out wafer level packaging processes that are larger than the chip.